Question: Does the synchronous exception handler in RISC-V use the same interrupt handler as the user software interrupt (ID=0)?
RISC-V Manual Volume II states that when in vectored mode, synchronous exceptions cause the PC to be set to the address in the BASE field, while interrupts cause the PC to be set to the address in the BASE field plus four times the interrupt cause number. To test this, code was written to trigger ecall, user software interrupt (ID=0) and machine timer interrupt on qemu-system-riscv64 virt.
After running the code, it appears that user software interrupts are not supported and are hardwired to 0 in the
mip CSRs. This means that the synchronous exception handler is not the same as the user software interrupt (ID=0) handler. There does not appear to be any conflict between the two.